These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the timedelay or monostable mode of operation, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor.The threshold and trigger levels normally are twothirds and onethird, respectively, of VCC. These levels can be altered by use of the controlvoltage terminal. When the trigger input falls below the trigger level, the flipflop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flipflop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flipflop is reset, and the output goes low. When the output is low, a lowimpedance path is provided between discharge (DISCH) and ground.The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5V supply, output levels are compatible with TTL inputs.